Curator's Take
This article introduces “routing codes,” a new family of quantum LDPC codes that retain high encoding rates while dramatically simplifying the connectivity requirements of superconducting chips and neutral‑atom arrays. By making all long‑range couplings parallel, the designs eliminate wiring crossings and reduce atom‑shuttling overhead, which addresses a major practical bottleneck that has limited previous high‑performance qLDPC proposals. The authors’ circuit‑level simulations show an eightfold reduction in physical qubits relative to surface codes for comparable logical error rates, suggesting a concrete path toward fault‑tolerant processors that can be built with today’s hardware constraints, though experimental validation will be needed to confirm the predicted gains.
— Mark Eatherly
Summary
Quantum low-density parity-check (qLDPC) codes are promising candidates for realizing large-scale fault-tolerant quantum computing. Although many codes with favorable theoretical parameters have been developed, their practical adoption must take hardware implementability into account. For mainstream quantum platforms such as superconductors and neutral atoms, the connectivity, the length of non-local couplings, and the complexity of wiring or atom rearrangement are key factors that dictate the difficulty of hardware realization. Here, we propose a new family of qLDPC codes, termed routing codes. Within this family, we find explicit instances whose encoding rates are comparable to those of bivariate bicycle (BB) codes, while systematically reducing qubit connectivity, shortening the length of non-local couplings, and, crucially, making all non-local couplings mutually parallel. This parallelism fundamentally eliminates wiring crossings in superconducting multi-layer architectures and drastically simplifies the scheduling of atom movement in neutral-atom arrays. Under circuit-level simulation, the weight-7 routing codes reduce the physical qubit overhead by approximately a factor of 8, compared to surface codes achieving a same logical error rate. These results establish routing codes as a hardware-centric qLDPC family that bridges the gap between theoretical optimality and near-term physical feasibility.