Curator's Take
AI Commentary
This article demonstrates a practical pathway to meet the microsecond‑scale decoding deadlines required for fault‑tolerant quantum computers by linking a QPU’s control system to high‑performance computing resources via the THQLink architecture, achieving an average round‑trip latency of just 2.9 µs and only 130 ns per additional network hop. By parallelising a matching‑based decoder on CPUs, the authors show real‑time decoding of surface‑code distances up to 19—far beyond current experimental demonstrations—and thus provide a scalable solution that could keep pace with the growing logical qubit counts envisioned for large‑scale devices. The work bridges the gap between quantum hardware and classical supercomputers, opening the door for more demanding hybrid algorithms and error‑correction workloads, while also highlighting that tight integration and low‑latency networking will be essential to avoid bottlenecks as systems scale further.
— Mark Eatherly
Summary
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 $μ$s on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 $μ$s per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.