Curator's Take
This research tackles one of the most practical challenges facing silicon quantum computing: how to manufacture hundreds or thousands of qubits with consistent behavior across a chip. The team's systematic study of 392 quantum dots across different oxide thicknesses reveals that there's a "sweet spot" at 17 nanometers that minimizes the random variations between qubits - a crucial finding since even small differences can make some qubits unusable or require complex calibration procedures. What makes this work particularly valuable is that it was conducted using industry-standard 300mm CMOS fabrication with extreme ultraviolet lithography, demonstrating that these insights can be directly applied to commercial quantum chip production. The discovery of optimal design parameters for reducing qubit variability brings silicon spin qubits closer to the uniform, large-scale arrays needed for fault-tolerant quantum computers.
— Mark Eatherly
Summary
Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.