Curator's Take
This research represents a major leap forward in quantum algorithm implementation, achieving unprecedented fidelity for the quantum Fourier transform on 50 qubits using IBM's Heron processor. The breakthrough comes from deploying the innovative Parity Architecture, which dramatically reduces the circuit depth and gate count compared to traditional swap-based approaches, leading to super-exponential improvements in performance scaling. While a fidelity of around 1% might seem modest, this represents the current frontier for large-scale quantum algorithms on noisy intermediate-scale quantum devices, where maintaining coherence across dozens of qubits remains extremely challenging. The work demonstrates that architectural innovations in how we map algorithms to quantum hardware can unlock performance gains that pure hardware improvements alone cannot achieve, pointing toward more efficient ways to run complex quantum algorithms as processors continue to scale up.
— Mark Eatherly
Summary
We demonstrate the Parity Architecture on quantum hardware, using the quantum Fourier transform (QFT) as a benchmark. As a result, a record performance in both fidelity and qubit count is achieved using quantum processors with a native CZ-based instruction set. On the IBM Heron r3 chip, a process fidelity of the QFT algorithm of ${F \approx 10^{-2}}$ for ${N=50}$ qubits is achieved. The scaling of the speedup compared to previous swap-based methods is super-exponential $\mathcal{O}(\exp(N^2))$. Furthermore, we show that the scaling can be improved further by including iSWAP gates in the instruction set.