Curator's Take
This breakthrough tackles one of quantum computing's most pressing challenges: how to scale beyond the physical limits of cramming qubits onto a single flat chip. By successfully demonstrating vertical stacking of qubit layers connected through a carrier chip, the researchers have opened a promising third dimension for quantum processor architecture while maintaining impressive gate fidelities above 97.5% for both same-layer and cross-layer operations. The ability to generate entangled states across different physical layers proves the approach works in practice, not just theory, potentially enabling the massive qubit counts needed for fault-tolerant quantum computers. This 3D integration approach could be the key to building quantum processors with thousands or even millions of qubits without being constrained by the real estate limitations of traditional planar designs.
— Mark Eatherly
Summary
Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit $W$ state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes.