Curator's Take
AI Commentary
This article tackles a key roadblock to scalable fault‑tolerant quantum computers by showing how neutral‑atom arrays can efficiently run high‑rate qLDPC product codes despite the notoriously hard compilation problem. By breaking a two‑dimensional scheduling task into optimal one‑dimensional subproblems and feeding those solutions through an anytime, movement‑aware pipeline, ONEX delivers provably depth‑optimal plans with dramatically reduced wall‑clock times. The reported 3.7–6.1× (and up to 42× for certain configurations) speedups in clock rate demonstrate that neutral‑atom platforms can now approach the throughput needed for practical quantum error correction, complementing recent advances in hardware connectivity and algorithmic code design. Readers should note that while the gains are impressive for hypergraph product codes, extending the approach to other QEC families will be an important next step.
— Mark Eatherly
Summary
Achieving fault-tolerant quantum computing at a practical scale demands quantum error correction (QEC) codes with high encoding rates. Quantum low-density parity-check (qLDPC) codes emerge as a promising candidate, especially given the rise of neutral atom arrays that provide dynamic long-range connectivity via atom movements. In general, synthesizing valid and efficient physical execution plans for QEC is a provably hard combinatorial problem, forming a critical compilation bottleneck that worsens as code sizes grow. To overcome this complexity, we focus on an important product family of qLDPC codes with dimension-reduction properties, and propose ONEX. This framework decomposes complex 2D physical execution planning into independent 1D subproblems, each solved to optimal execution depth within practical compilation time. First, we formulate the 1D execution plan with an explicit satisfiability modulo theories (SMT) encoding. This protocol produces provably depth-optimal solutions with substantial duration reduction. Second, we develop a multi-stage compilation pipeline featuring anytime optimization, movement compaction, and iterative feedback. This pipeline maintains practical wall-clock times while providing progressive refinement and on-demand retrieval of quality solutions. Third, we evaluate ONEX in the application of hypergraph product (HGP) code memory mapped onto neutral atom arrays, achieving 3.7x to 6.1x and 29.8x to 42.1x higher clock rates than the constructive 1D algorithm and the general 2D compiler, respectively, while scaling efficiently to codes with 2,500 data qubits. Finally, we extend ONEX to zoned layouts, revealing architectural insights into the associated trade-offs, and demonstrate its applicability to the broader lifted-product (LP) code family through a representative example.