Curator's Take
AI Commentary
This article shows that the long‑standing bottleneck of slow logical measurements in high‑rate quantum LDPC codes can be overcome with a surprisingly simple resource—cat states—by jointly measuring many commuting operators and using a scheduler code to decode them efficiently. The reported threefold speed‑up for 20‑operator measurements, and up to 74× acceleration for random Clifford circuits when combined with the CliNR partial error‑correction scheme, brings LDPC‑based fault tolerance into a regime where it can compete with surface‑code runtimes while retaining its much lower qubit overhead. If these gains hold in larger architectures, they could dramatically shorten the time needed for logical gate sequences and make near‑term quantum processors more viable for practical algorithms that demand both high fidelity and low latency.
— Mark Eatherly
Summary
Quantum LPDC codes provide a substantial reduction in qubit overhead required for fault-tolerant quantum computation compared to surface code, thanks to their high encoding rate. However, operating simultaneously on multiple logical qubits encoded in the same block is more challenging and may slow down logical operations. Prior work addresses this problem by designing complex resource states to perform logical measurements in LDPC codes. Here, we propose an approach that only consumes cat states. Whereas previous work on cat-based measurements focuses on a single logical measurement, we design a protocol for the joint measurement of $\ell$ commuting logical operators. The key ingredient is the design of a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 of the walking cat architecture show a speed-up of nearly $3\times$ over Viterbi measurements for the measurement of $\ell=20$ commuting logical operators. Combining our fast logical measurements with a new variant of the CliNR partial error correction scheme, we achieve a speed up of up to up to $74\times$ for random Clifford circuits. Our approach also applies to non-Clifford gates, producing a speed up of up to $5\times$ for Toffoli gates.