Curator's Take
This article tackles a pressing bottleneck for NISQ‑era variational algorithms by quantifying the trade‑off between circuit depth and iteration count, offering a concrete “sweet spot” that delivers a target accuracy with the fewest gate operations. By grounding their phenomenological model in VQE simulations and extending it to error‑mitigated hardware, the authors provide a practical design rule that complements recent work on noise‑aware ansatz selection and adaptive measurement strategies. If adopted, the methodology could streamline resource budgeting for near‑term quantum chemistry and materials studies, though its accuracy will still hinge on how well the simplified noise model captures device‑specific error correlations.
— Mark Eatherly
Summary
For quantum algorithms to achieve their full potential, we need methodologies to optimize them, such as reaching a given output accuracy with minimal resource costs. Here, we develop such a methodology for a class of Noisy Intermediate-Scale Quantum (NISQ) algorithms. We leverage simulations of a Variational Quantum Eigensolver (VQE) to propose a phenomenological model of such algorithms that captures the complex relationship between algorithmic accuracy, algorithmic resource costs, and the noise that exists in realistic quantum hardware. For this, we take the algorithmic resource cost to be the total number of quantum gate-operations in the algorithm; minimizing this cost typically makes the algorithm faster and more energy-efficient. We consider the subtle trade-off between quantum circuit size (small circuits are too imprecise, but large ones are too noisy), and the number of iterations of that quantum circuit for the full algorithm to sufficiently converge. Using a noise-metric-resource methodology, we identify the sweet spot (of circuit size versus iterations) that minimizes the algorithmic resource costs for a desired algorithm accuracy. It also gives the circuit size that maximizes algorithm accuracy for a fixed resource cost. Our methodology provides a practical guideline for near-term deployment of variational algorithms on realistic noisy hardware, including hardware that uses error mitigation.