Curator's Take
This article tackles one of the most pressing challenges in early fault-tolerant quantum computing: how to efficiently execute circuits when your quantum operations are inherently probabilistic and time-consuming. The researchers develop a clever protocol for the STAR architecture that parallelizes the creation of resource states and optimizes their allocation using classical optimization techniques, potentially reducing the massive time overhead that typically plagues repeat-until-success protocols in surface code implementations. What makes this particularly valuable is their performance prediction framework that can help determine optimal qubit topologies without running expensive full simulations - a practical tool that could significantly accelerate the development and deployment of early fault-tolerant quantum algorithms as the field transitions from noisy intermediate-scale devices to logical qubit systems.
— Mark Eatherly
Summary
As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates $Rz(θ)$ as non-Clifford gates instead of $T = Rz(π/4)$. $Rz(θ)$ operations involve creation of resource states $|m_θ\rangle = \frac{1}{\sqrt{2}} (|0 \rangle + e^{iθ} |1\rangle ) $ followed by ZZ joint measurements with target logical qubits. While employing $Rz(θ)$ enables more efficient circuit execution, both their creations and joint measurements are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient. Furthermore, we proposed performance estimators given the target circuit and qubit topology. It successfully predicts the time performance within less time than actual simulations do, and helps find the optimal qubit topology to run the target circuits efficiently.