hardware error_correction

Trapped-Ion Multiqubit Gates are Compatible with Scalable Quantum Error Correction

Curator's Take

This research tackles one of the most critical questions in quantum computing: whether multi-qubit gates in trapped ion systems can maintain low enough error rates to enable practical quantum error correction. The team's detailed noise modeling reveals that while errors can theoretically spread between any qubits due to trapped ions' all-to-all connectivity, the actual error rates between non-participating qubits remain manageable - a crucial finding for scaling up these systems. By directly connecting device-level physics to quantum error correction performance using the surface code, this work provides a concrete roadmap for determining how large trapped ion quantum computers can realistically become before noise overwhelms the error correction benefits. This represents exactly the kind of rigorous, end-to-end analysis needed to bridge the gap between today's noisy intermediate-scale quantum devices and tomorrow's fault-tolerant quantum computers.

— Mark Eatherly

Summary

We construct a detailed microscopic noise model for multi-qubit (MQ) gate operations in the context of trapped ion architecture with all-to-all connectivity. We find that phonon heating and motional dephasing are well captured by effective single- and two-qubit error channels that can, in principle, act between arbitrary pairs of qubits. Nevertheless, the median magnitude of two-qubit errors between uncoupled qubits is substantially smaller than that of errors between gate-coupled qubits. Errors associated with photon scattering are shown to solely propagate to qubits participating in gate operations. Lastly, we combine all noise sources, assigned with experimentally relevant parameters, and explore the scalability of a quantum error correction (QEC) scheme based on the rotated surface code, as a function of error rates and code size. Our analysis bridges device-level physics and QEC performance for MQ gates in trapped-ion architectures.