Curator's Take
This article introduces a superconducting soliton DAC that converts trapezoidal drive pulses into nanosecond flux bursts, enabling 5.6 ns S‑gates on transmons with an excitation error below 0.05% and no measurable impact on the qubit’s intrinsic T₁. By filtering control noise, providing native multiplexing and being CMOS‑compatible, the DAC tackles a key scaling bottleneck in microwave‑driven quantum processors and dovetails with recent pushes toward cryogenic control electronics. The ability to perform fixed‑time, high‑fidelity gates that are robust against fabrication variance could accelerate the integration of dense qubit arrays, though the observed 1.6 % non‑local phase error on untargeted ancilla qubits highlights a need for further isolation or overdamping refinements before large‑scale deployment.
— Mark Eatherly
Summary
We introduce a superconducting digital-to-analog converter (DAC) that filters control noise, provides native multiplexing, performs quantum gates in nanoseconds, and can be controlled by CMOS. This is achieved by transducing a trapezoidal drive pulse into a superconducting soliton, which is then held in the DAC load loop, applying flux to a mutually-coupled superconducting qubit or gate coupler. The analog flux output by the DAC can be easily controlled by varying the soliton hold time, or with a DC-biased tunable DAC-qubit coupler, allowing the DAC to perform a fixed-time, high-fidelity gate that's robust to fabrication variance or flux offsets in the quantum circuit. Our initial demonstration shows that the DAC can successfully perform 5.6 ns S-gates on transmons. We measure the DAC-induced quantum state excitation probability per gate to be 0.05%, and find that the DAC-induced relaxation rate from the qubit 1 state is below the intrinsic T1 rate limit of the transmon. Quantum simulations show qualitative agreement with the measured data, and predict that the DAC excitation rate can be lowered 10 times further by overdamping the Josephson junction (JJ) in the DAC load loop. may be limited by a Interleaved Randomized Benchmarking (IRB) sequences on an observer qubit reveal that, when scaling to many qubits, the DAC's performance may be limited by a non-local, DAC-induced phase error of 1.6% per gate, appearing in ancilla qubits that are not directly coupled to any of the 30 DACs on the chip. We discuss strategies for future layouts of multi-DAC chips that focus on mitigating the source of these non-local, high-frequency electromagnetic interactions (EMI), and how to incorporate a DC-tunable coupler for phase correction.