Curator's Take
This breakthrough represents a major step toward practical quantum error correction by achieving real-time feedback with ultra-low latency of just 550 nanoseconds on actual quantum hardware. The FPGA-based neural network decoder successfully keeps pace with the quantum processor's error correction cycle, demonstrating that classical processing can match the speed requirements for fault-tolerant quantum computing. Most significantly, the team showed their system works during mid-circuit corrections in complex quantum algorithms where traditional error correction methods fall short, proving the approach scales beyond basic demonstrations. This hardware-integrated architecture provides a concrete pathway for building the fault-tolerant quantum computers needed for practical quantum advantage in fields like cryptography and drug discovery.
— Mark Eatherly
Summary
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.